STC’s Combinatorial Technologies (Formally The REBUS Project)

Overview

STC’s combinatorial architecture is a very elegant design and solution that solves most of the challenges implementing new Internet capabilities such as multicasting, scalability of high-performance networks, and QoS. With its disruptive technology and OEM products, STC delivers advanced scalability at a cost effective price point to better position device manufactures for the emergence of the "Next Generation Internet" (NGI) as well as those faced by the microprocessor industry. These technology elements initially developed at The George Washington University, work independently and without a “master conductor” who arranges the work.

IP Multicasting: Typical routers are designed to move each IP packet from an input channel to one of the output channels. In large volumes/data streams this process requires intensive processing activities or application-specific integral circuits for switching. The switching in turn needs control (intense computation) which is performed “real time”.

With STC’s routing architecture, the routing is accelerated and simplified using data replication with a direct match of each IP data packet. From an “information” processing stand point, the two stages of the routing process merge (computation with routing). With the advantages of efficiency and enhanced computation, combined with packet replication enables STC’s multicast processing.

Other architectural benefits include: 

·         IPv4 & IPv6 capable/packet agnostic

·         Better resistance to overloads/Denial of Service (DoS) attacks

·         Effectual pre-processing scheduling using bare wires

·         Simplified multicast implementation

·         Simplifying performance or reliability.

How it works

The following diagram below is a schematic of the simplest depiction of STC’s combinatorial architecture. Following any course on this diagram, processing (or routing) elements can reach any of the 7 outputs (represented by triangles) from any of the 7 inputs (represented by circles). With the combination of any relationship of “inputs and outputs” (triangles & circles) – one processing node (represented by squares) is created for computation. A data transmission can not be preformed better, faster and more efficient than reducing the use of any active elements and computing at “bare wire” speeds. The product form of this architecture is to hook all the inputs and all the outputs on a single processor or multi-cast routing application within a single FPGA.

STC’s SNAPP Router

The SNAPP Routing Core has a noticeable property which differentiates it from any existing switching routers based on ATM - an ability to route broadcast and multicast traffic with no latency and no copying overhead. Such broadcasts can be performed at the full speed of all output channels.

The router is a straightforward implementation of such principles. Assume a packet came from the input interface I2 and should be routed to the interface O5. The interface I2 is connected to the processing units PE2, PE3 and PE5 with the line 2. All of the units listed start search the route to the destination in their routing tables. Processing units PE2 and PE3 fail as they have no route to O5. PE5 has the route listed in its routing table and it forwards the packet received to the O5.

Due to the distributed nature of processing the suggested design has better resistance to overloads while Denial of Service (DoS) attacks or global routing instability. While overload of any of the channels is fatal for a traditional single-processor, shared-bus and shared-memory router, SNAPP router remains mostly operational even some of the channels and PEs get clogged.

The SNAPP Processor

Current implementations of HPC equipment and technology require a high capital investment in hardware. With its new disruptive technology and products, STC can significantly reduce the high dollar capital investment in hardware. By targeting the PLD market, the result is the expansion of the overall market with PLD based HPC market. STC’s exclusive combinatorial feature will bring scalability and flexibility as well as a much shorter time to market for prospective customers.

Using a specialized network of fundamental processing elements, a new PLD based HPC technology will emerge with STC’s FPGA Processor. The SNAPP Processor Core is a break-through in processor technology leveraging combinatorial processing element architecture. The SNAPP core is an EPIC (Explicitly Parallel Instruction Computing) processor which can facilitate instruction and sub-instruction level computational parallelism. Using the SNAPP architecture, customers will be able to scale computational power to meet their demands by seamlessly linking the SNAPP cores together to create a mesh of processors (or routers) which will operate as one.

•            Many Operate As One                                               Other Benefits:

•            Combinatorial or Stand Alone                                    Improved Dissipation Of Heat

•            Unlimited  Processing Scalability                               Power Consumption

          SNAPP Overview

          SNAPP Processor  

           White Paper

  SNAPP Router

          White Paper